1. Technical Field
This disclosure relates to delay circuitry and more particularly, to an apparatus for trimming a frequency range for a data path using delay locked loop circuits which may be employed with down sort capability.
2. Description of the Related Art
Delay locked loops (DLL) are employed to compare a periodic signal input signal with an output signal. In this way a phase difference between the signals can be set to about zero. Referring to FIG. 1, a conventional DLL 10 is shown. An input signal CKin is input to a delay line 12 and a phase comparator 14. An output signal CKout is compared with input signal CKin by employing phase comparator 14. Phase comparator 14 sets or adjusts delay line 12 to provide a zero phase difference between the input and output signals. Delay line 12 stabilizes when the delay between input CKin and output CKout signals reaches a clock period T or a multiple thereof (kT, where k is a natural number). DLL 10 may be employed to synchronize an input clock to an output clock on a given integrated circuit, for example.
Referring to FIG. 2, an application of a DLL is shown. DLL 20 includes delays introduced by a receiver 22 and by a driver 24. These delays are compensated for by a delay element 26. Delay element 26 provides a delay compensation of .tau. in a feedback loop where .tau.=R+D. R is the delay introduced by receiver 22, and D is the delay introduced by driver 24. Input and output clocks, CKin and CKout, respectively, are synchronized when their phase difference becomes 2k.PI., that is, when the delay between input and output signals is equal to a multiple of the clock period, i.e., kT. Then, phase comparator 14 detects no phase difference between its two inputs 25 and 27. Input 25 has a delay of R compared to input clock (CKin). Input 27 has a delay of kT+R compared to input clock (CKin), where T is the clock period. In the case shown and described with respect to FIG. 2, the delay line control signal (pointer) 30 is adjusted until inputs 25 and 27 are in sync.
Referring now to FIG. 3, a more specific use for a DLL is illustrated. A circuit 40 is employed to synchronize an output data stream DQout. Output data DQ is latched in a D Flip Flop (DFF) by a DLLCLK signal. The delay is the sum of receiver delay R, driver delay D and the delay introduced by Flip Flop DFF.
A frequency range for a delay locked loop (DLL) can be evaluated according to the following. A maximum frequency of a DLL corresponds to the minimum delay line delay D.sub.min associated with a smallest value of a pointer (30 in FIG. 3). kT=R+D.sub.min +D of f.sub.max =k/(R+D.sub.min +D). High frequencies may be obtained by increasing the speed of receiver 22 and/or a data path by reducing D.sub.min, the insertion delay of the delay line 12 or by synchronizing to a multiple of the period T. Operation at high frequency implies that the delay introduced by the delay line is small. This means the delay step should be chosen to be very small to reduce jitter.
The minimum frequency of the DLL corresponds to the maximum delay of delay line 12, D.sub.max associated with the highest value of the pointer. kT=R+D.sub.max +D or f.sub.min =k/(R+D.sub.max +D).
For some purposes, low frequency operation is necessary. Joint Electron Device Engineering Council (JEDEC) requires devices to be operational at 1/2 the nominal frequency (See JC-42.3C Subcommittee on RAM Timing and Parametrics, Albuquerque, N. Mex., Jun. 3, 1998). For example, a 100 MHz chip should be able to run at 50 MHz. This requirement is in contradiction with the high frequency operation of the chip. For high frequency operation, the delay elements included in delay line 12 have to be very small so that minimum jitter is introduced by the delay line adjustment during chip operation. For low frequency operation, the delay introduced by delay line 12 has to be very high. Since the unit delay has to be very small, a very long delay line has to be used for this purpose. In the case of a digital DLL, more control bits are needed for the correct operation (more bits for the pointer signal). Also, more layout area for the delay line is needed on the chip. The JEDEC requirement for lower frequency operation is especially difficult to meet if the chip has devices (transistors) with short channel lengths. With short channel devices in the delay units, the unit delay of each delay line element is smaller which means that the total delay that can be introduced by the delay line will get smaller, which means that the minimum frequency of operation will increase.
Referring to FIG. 4, a typical delay line circuit 70 is shown. Delay line 70 includes delay control lines 72 which input a digital word generated by phase comparator 14 (FIGS. 1-3). The digital word enables appropriate multiplexers 74 which are 2:1 multiplexers. Multiplexers 74 are arranged hierarchically according to the place value of the digital word. A delay line input (IN) receives a periodic signal, such as a clock signal and applies the signal to a plurality of delay units 76. Delay units 76 include a pair of invertors 78 for providing an appropriate delay to the input periodic signal. The invertors are powered by a constant voltage source. The number of delay units 76 employed in delay line 70 is set by multiplexers 74 which are activated by the digital word on control lines 72. The 2:1 multiplexers 74 complete a circuit from input (IN) to an output (OUT) through a predetermined number of inverter pairs to provide an appropriate delay such that the input and the output signals are substantially in sync.
Therefore, a need exists for a delay line which permits both high and low frequency operation by varying a supply voltage to delay elements of the delay line. A further need exists for a delay locked loop circuit which utilizes the delay line in integrated circuits.